1. Field of the Invention
The present invention relates to a wiring substrate based on a TSV (through-silicon-via) technology and a manufacturing method therefor. More particularly, it relates to a wiring substrate based on a narrow-pitch TSV technology and a manufacturing method therefor.
2. Description of the Related Art
In order to realize a three-dimensional wiring substrate based on a TSV (through-silicon-via) technology, through electrodes have to be electrically insulated from a silicon substrate. As a means for electrical insulation, Japanese Unexamined Patent Application Publication No. 2008-251964 discloses a technology of providing a ring-shaped isolation groove passing through a silicon substrate and surrounding a through electrode, forming silicon films directly on bottom and side faces of the isolation groove, forming an insulation film on the silicon films so as to fill a space left in the isolation groove, and then thermally oxidizing the surface of the silicon films in contact with inner and outer peripheral side faces of the isolation groove so as to form a thermally oxidized silicon film.
However, since a sufficiently thick insulation film is difficult to form, a metallic component constituting the through electrode, e.g., Cu may be dispersed in the silicon oxide film and the silicon substrate, impairing the electrical insulating properties. Also, cracks may be formed in the insulation film, impairing the insulating properties.
Japanese Patent No. 5225479 discloses a technology effective in solving the above-described problems. The wiring substrate manufacturing method disclosed in Japanese Patent No. 5225479 includes an insulating layer formation process and a columnar conductor formation process. In the insulating layer formation process, a hole or groove is formed in a semiconductor substrate along its thickness direction and an insulating layer is formed in the hole or groove. In the columnar conductor formation process, a hole or groove is formed in a region surrounded by the insulating layer and a vertical columnar conductor containing a metal/alloy component is formed in the hole or groove.
According to the technology disclosed in Japanese Patent No. 5225479, it is possible to produce an insulator having excellent physical and chemical strength, a reliable insulator free from defects such as a gap, a void or a crack, and an insulator having various electrical properties.
However, Japanese Patent No. 5225479 does not disclose a narrow-pitch TSV technology, i.e., technology of forming a lot of vertical columnar conductors at a narrow pitch. When the arrangement pitch of the vertical columnar conductors is equal to or less than 4 μm, for example, even a slight misalignment of grooves or holes, in which the vertical columnar conductors are to be formed, may easily cause a failure such as poor connection. Japanese Patent No. 5225479 fails to disclose a means for preventing the occurrence of such a failure.
When TSVs are formed at a narrow pitch, moreover, the cross sectional area of columns to be used for supporting the vertical columnar conductors or insulators during the manufacturing process becomes too small, which may cause various failures during the manufacturing process, e.g., breakage of columns, misalignment of columns, or contact between columns. Japanese Patent No. 5225479 also fails to disclose a means for preventing the occurrence of such a failure.